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5.4 a. Using λf = c, we have λ = (3 × 108 m/sec)/(300 Hz) = 1,000 km, so that
λ/2 = 500 km.
b. The carrier frequency corresponding to λ/2 = 1 m is given by:
f = c/λ = (3 × 108 m/sec)/(2 m) = 150 MHz.

5.8 LdB = 20 log(fMHz) + 120 +20 log (dkm) + 60 – 147.56
= 20 log(fMHz) +20 log (dkm) + 32.44

5.12 From Equation 2.2, the ratio of transmitted power to received power is
Pt/Pr = (4πd/λ)2
If we double the frequency, we halve λ, or if we double the distance, we double d,
so the new ratio for either of these events is:
Pt/Pr2 = (8πd/λ)2
Therefore:
10 log (Pr/Pr2) = 10 log (22) = 6 dB

5.16 a. Output waveform:
sin (2πf1t) + 1/3 sin (2π(3f1)t) + 1/5 sin (2π(5f1)t) + 1/7 sin (2π (7f1)t)
where f1 = 1/T = 1 kHz
Output power = 1/2 (1 + 1/9 + 1/25 + 1/49) = 0.586 watt
b. Output noise power = 8 kHz × 0.1 μWatt/Hz = 0.8 mWatt
SNR = 0.586/0.0008 = 732.5 (SNR)dB = 28.65

6.4 Eb/N0 = (S/N) (B/R)
S/N = (R/B) (Eb/N0) = 1 × (Eb/N0)
(S/N)dB = (Eb/N0)dB
For FSK and ASK, from Figure 4.10, (Eb/N0)dB = 13.5 dB
(S/N)dB = 13.5 dB
For PSK, from Figure 4.10, (Eb/N0)dB = 10.5
(S/N)dB = 10.5 dB
For QPSK, the effective bandwidth is halved, so that
(R/B) = 2
(R/B)dB = 3
(S/N)dB = 3 + 10.5 = 13.5 dB

6.8 No. The demodulator portion of a modem expects to receive a very specific type of
waveform (e.g., ASK) and would not produce meaningful output with voice input.
Thus, it would not function as the coder portion of a codec. The case against using a
codec in place of a modem is less easily explained, but the following intuitive
argument is offered. If the decoder portion of a codec is used in place of the
modulator portion of a modem, it must accept an arbitrary bit pattern, interpret
groups of bits as a sample, and produce an analog output. Some very wide value
swings are to be expected, resulting in a strange-looking waveform. Given the
effects of noise and attenuation, the digital output produced at the receiving end by
the coder portion of the codec will probably contain many errors.

6.12 a. A total of 28 quantization levels are possible, so the normalized step size is 2–8
= 0.003906.
b. The actual step size, in volts, is:
0.003906 × 10V = 0.03906V
c. The maximum normalized quantized voltage is 1 - 2-8 = 0.9961. Thus the actual
maximum quantized voltage is:
0.9961 × 10V = 9.961V
d. The normalized step size is 2–8. The maximum error that can occur is one-half
the step size. Therefore, the normalized resolution is:
+ 1/2 × 2–8 = 0.001953
e. The actual resolution is
+ 0.001953 × 10V = + 0.01953V
f. The percentage resolution is
+ 0.001953 × 100% = + 0.1953 %

6.16 a. For AM, s(t) = [1 + m(t)] cos(2πfct)
s1(t) = [1 + m1(t)] cos(2πfct); s2(t) = [1 + m2(t)] cos(2πfct)
For the combined signal mc(t) = m1(t) + m2(t),
sc(t) = [1 + m1(t) + m2(t)] cos(2πfct) = s1(t) + s2(t) – 1, which is a linear
combination of s1(t) and s2(t).
b. For PM, s(t) = A cos(2πfct + npm(t))
s1(t) = A cos(2πfct + npm1(t)); s2(t) = A cos(2πfct + npm2(t))
For the combined signal mc(t) = m1(t) + m2(t),
sc(t) = A cos(2πfct + np[m1(t) + m2(t)]), which is not a linear combination of s1(t)
and s2(t).

7.4 a. Period of the PN sequence is 24 – 1 = 15
b. MFSK
c. L = 2
d.M = 2L = 4
e. k = 3
f. slow FHSS
g. 2k = 8
h.

Time	0	1	2		3	4		5	6		7	8		9	10		11
Input data	0	1	1		1	1		1	1		0	0		0	1		0
Frequency	f1			f3			f3			f2			f0			f2

Time	12	13	14		15	16		17	18		19
Input data	0	1	1		1	1		0	1		0
Frequency	f1			f3			f2			f2

7.12 a.

State	B4	B3	B2	B1	B0	B0 ⊕ B3	output
0	1	0	0	0	0	0	0
1	0	1	0	0	0	1	0
2	1	0	1	0	0	0	0
3	0	1	0	1	0	1	0
4	1	0	1	0	1	1	1
5	1	1	0	1	0	1	0
6	1	1	1	0	1	0	1
7	0	1	1	1	0	1	0
8	1	0	1	1	1	1	1
9	1	1	0	1	1	0	1
10	0	1	1	0	1	0	1
11	0	0	1	1	0	0	0
12	0	0	0	1	1	1	1
13	1	0	0	0	1	1	1
14	1	1	0	0	0	1	0
15	1	1	1	0	0	1	0
16	1	1	1	1	0	1	0
17	1	1	1	1	1	0	1
18	0	1	1	1	1	0	1
19	0	0	1	1	1	1	1
20	1	0	0	1	1	1	1
21	1	1	0	0	1	0	1
22	0	1	1	0	0	1	0
23	1	0	1	1	0	0	0
24	0	1	0	1	1	0	1
25	0	0	1	0	1	1	1
26	1	0	0	1	0	0	0
27	0	1	0	0	1	0	1
28	0	0	1	0	0	0	0
29	0	0	0	1	0	0	0
30	0	0	0	0	1	1	1
31=0	1	0	0	0	0	0	0

State	B4	B3	B2	B1	B0	B0 ⊕ B1 ⊕ B3 ⊕ B4	output
0	1	0	0	0	0	1	0
1	1	1	0	0	0	0	0
2	0	1	1	0	0	1	0
3	1	0	1	1	0	0	0
4	0	1	0	1	1	1	1
5	1	0	1	0	1	0	1
6	0	1	0	1	0	0	0
7	0	0	1	0	1	1	1
8	1	0	0	1	0	0	0
9	0	1	0	0	1	0	1
10	0	0	1	0	0	0	0
11	0	0	0	1	0	1	0
12	1	0	0	0	1	0	1
13	0	1	0	0	0	1	0
14	1	0	1	0	0	1	0
15	1	1	0	1	0	1	0
16	1	1	1	0	1	1	1
17	1	1	1	1	0	1	0
18	1	1	1	1	1	0	1
19	0	1	1	1	1	1	1
20	1	0	1	1	1	1	1
21	1	1	0	1	1	0	1
22	0	1	1	0	1	0	1
23	0	0	1	1	0	1	0
24	1	0	0	1	1	1	1
25	1	1	0	0	1	1	1
26	1	1	1	0	0	0	0
27	0	1	1	1	0	0	0
28	0	0	1	1	1	0	1
29	0	0	0	1	1	0	1
30	0	0	0	0	1	1	1
31=0	1	0	0	0	0	1	0

8.4 At the conclusion of the data transfer, just before the CRC pattern arrives, the shift
register should contain the identical CRC result. Now, the bits of the incoming
CRC are applied at point C4 (Figure 8.3). Each 1 bit will merge with a 1 bit
(exclusive-or) to produce a 0; each 0 bit will merge with a 0 bit to produce a zero.

8.8 a. For simplicity, we do not show the switches.

C4	C3	C2	C1	C0	C4 ⊕ C3	C4 ⊕ C1	C4 ⊕ I	Input
0	0	0	0	0	0	0	1	1
0	0	0	0	1	0	0	0	0
0	0	0	1	0	0	1	1	1
0	0	1	0	1	0	0	0	0
0	1	0	1	0	1	1	0	0
1	0	1	0	0	1	1	1	0
1	1	1	0	1	0	1	0	1
0	1	1	1	0	1	1	1	1
1	1	1	0	1	0	1	1	0
0	1	1	1	1	1	1	1	1
1	1	1	1	1	0	0	1	–
0	1	0	1	1	1	1	0	–
1	0	1	1	0	1	0	1	–
1	1	0	0	1	0	1	1	–
0	0	1	1	1	0	1	0	–
0	1	1	1	0

c. The partial results from the long division show up in the shift register, as indicated by the shaded portions of the preceding table. Compare to long division example in Section 8.1. d. Five additional steps are required to produce the result.

8.12
C1 = D1 ⊕ D2 ⊕ D4 ⊕ D5 ⊕ D7
C2 = D1 ⊕ D3 ⊕ D4 ⊕ D6 ⊕ D7
C4 = D2 ⊕ D3 ⊕ D4 ⊕ D8
C8 = D5 ⊕ D6 ⊕ D7 ⊕ D8

8.16 Need n – k check bits such that 2(n – k) – 1 ≥ 1024 + (n – k).
The minimum value of n – k that satisfies this condition is 11.

8.20
a.

8.24 Round trip propagation delay of the link = 2 × L × t Time to transmit a frame = B/R To reach 100% utilization, the transmitter should be able to transmit frames continuously during a round trip propagation time. Thus, the total number of frames transmitted without an ACK is: